Engineering
8 years ago

Efficient 64-bit Adder Design Saves Power, Boosts Arithmetic Performance.

Implementation of an efficient 64-bit Carry Select Adder using muxes
Rahul Chandran G, N. Saraswathi

Paper Summary

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The article presents a new way to make adder circuits more efficient by using a modified full adder in a Square root Carry Select Adder (CSLA). This method helps save power and improve performance in arithmetic operations. The researchers replaced a component called Ripple Carry Adder with a Binary to Excess One converter to make the CSLA smaller and more effective. The study shows that this modified approach can be used in 8, 16, 32, and 64-bit CSLAs to achieve better power savings compared to current systems.