New methods ensure high-level system designs are verified automatically and accurately.
The article discusses how designers use high-level languages like C, SystemC, and SystemVerilog for system-level design to handle the increasing complexity of Systems on Chip (SOC). The focus is on high-level verification techniques that ensure properties verified in the high-level design are preserved in the low-level Register Transfer Language (RTL) design. By combining formal techniques, designers can automatically verify system designs and check for equivalence between high-level specifications and their refined implementations. This approach allows for scalable verification of system designs and enables early exploration of system-level designs.
