The researchers designed and implemented a Carry Select Adder with alternate techniques to reduce area, delay, and power consumption. They used a Square-root CSLA to decrease carry propagation delay and a multiplexer-based add one circuit to reduce area with minimal speed penalty. The modified square-root CSLA showed improved outcomes compared to regular linear and square-root CSLA systems. The 128-bit modified Linear CSLA had similar size ripple carry adders in each group, resulting in decreased area for 128-bit sizes without sacrificing performance.