The article describes a verification platform using UVM to test designs quickly. It doesn't use UVM's reference model verification component and is suitable for modules without algorithm models. The platform uses a hierarchical register model for flexible configuration. The platform successfully verified an Interrupt handling module based on the AXI high-speed bus transmission protocol, showing full and overflow of ring FIFO and meeting protocol requirements. The coverage rate also met verification requirements, proving the platform's flexibility and reusability. Chip verification is crucial for chip development, ensuring smooth tapeout.