A modified carry select adder was designed to be more efficient in terms of area usage. Instead of using multiple Ripple Carry Adders, this new design uses a Binary to Excess -1 converter and Basic unit to reduce the number of logic gates needed. The result is a carry select adder that takes up less space while still performing fast arithmetic operations. The new design was tested using modelsim and was found to occupy 35 LUT's, showing that it is better than the traditional carry select adder in terms of area efficiency. However, it may cause a slight increase in delay.